The present invention relates to apparatus and methods for high voltage transistors. More specifically, this invention relates to apparatus and methods for high voltage MOS transistors with a gate extension.
Many applications for semiconductor devices require MOS transistors that can operate with high voltages (e.g., greater than 40 volts) at their terminals. At a high drain-to-source voltage and a low gate voltage, the voltage drop between the drain and the gate of an MOS transistor across the gate oxide can produce a large electric field in the portion of the drain that is underneath the gate. If the gate overlaps the drain in a small area and the gate oxide layer is thin, the large electric field can cause a high impact generation rate of carriers that may result in hot carrier injection and breakdown. Hot carrier injection can cause carriers to become trapped in the gate oxide causing the threshold voltage of the transistor to change, which is undesirable. Breakdown may cause undesirable parasitic currents and device failure. A large electric field can also increase stress on the gate oxide layer increasing the chances of a device failure.
One previously known high voltage MOS transistor 10 is shown in FIG. 1A. In transistor 10, thick field oxide 11 is formed over N-type drain region 13, and a portion of gate 12 of transistor 10 is formed along the upper edge of thick field oxide 11 as shown in FIG. 1A. Thick field oxide 11 reduces the electric field in N-type drain region 13 below gate 12 to reduce the high impact generation rate of carriers. However, thick field oxide 11 causes transistor 10 to have undesirably large device dimensions. Thick field oxide 11 also increases the resistance between the drain-to-source (RDS-ON) which is also undesirable, because field oxide 11 encroaches down into N-type drain region 13. A further disadvantage of transistor 10 is that the N-type doping concentration in N-type drain region 13 is higher near bird""s beak 11A of thick oxide 11 than the N-type doping concentration near the lower boundary 11B of thick oxide 11. This effect causes an increased electric field under the gate which is also undesirable.
Another previously known high voltage MOS transistor 20 is shown in FIG. 1B. Transistor 20 has N-type extension region 22 which is an extension of the drain region of the transistor. N-extension 22 has a lower N-type doping concentration than highly doped N+ drain region 24. N-extension 22 increases the drain-to-body breakdown voltage in transistor 20. However, the peak electric field on the drain side is high at a high drain-to-source voltage. The high electric field in N-extension 22 may cause hot carrier injection in gate oxide 26.
Another previously known high voltage MOS transistor 30 is shown in FIG. 1C. Transistor 30 has gate oxide 36 and gate 32. Gate oxide 36 has a thick portion 36A that extends over N-extension region 22 as shown in FIG. 1C. Gate 32 of transistor 30 has a stepped portion 32A that extends over a portion of thick portion 36A of gate oxide 36. Transistor 30 has a reduced electric field and a reduced impact generation rate of carriers in N-extension 22 at high drain voltages. Transistor 30 requires additional process steps relating to the formation of thick oxide portion 36A that are not typically used in standard CMOS and BiCMOS processes. These additional steps increase the complexity and time associated with the fabrication of MOS transistor 30.
It would, however, be desirable to provide a MOS transistor that can operate at high voltages with a reduced peak electric field in the drain so that the impact generation rate is not high enough to cause breakdown or substantial hot carrier injection. It would further be desirable to provide a high voltage MOS transistor that can be fabricated with process steps that are standard in CMOS and BiCMOS processes.
It is an object of the present invention to provide a MOS transistor that can operate at high voltages with a reduced peak electric field in the drain so that the impact generation rate is not high enough to cause breakdown or substantial hot carrier injection.
It is also an object of the invention to provide a high voltage transistor that can be fabricated with process steps that are standard in CMOS and BiCMOS processes.
These and other objects of the present invention are provided by high voltage transistors with a gate extension. The present invention also includes methods for using and making high voltage transistors with a gate extension. The high voltage transistor with gate extension of the present invention includes a first and second gate layers, and a dielectric layer between the gate layers. The first and second gate layers are electrically coupled together by being in direct physical contact with each other or through another electrically conducting layer such as a metal contact. The first and second gate layers form the gate of the transistor. The first and second gate layers may be electrically coupled together over the active area of the device or over the field oxide region.
The first gate layer is disposed on the gate oxide layer. The second gate layer is disposed above at least a portion of the first gate layer. The second gate layer extends over the drain of the transistor above the dielectric and gate oxide layers to form the gate extension. The thickness of the gate extension can be reduced to form a stepped gate extension. The gate extension reduces the peak electric field in the drain near the gate by providing a wide area for the voltage to drop between the drain and the gate of the transistor. The dielectric layer also contributes to reducing the peak electric field in the gate side of the drain by providing insulation between the gate and the drain. The dielectric layer also reduces the parasitic gate-to-drain capacitance.
Many analog CMOS and BiCMOS processes provide dual polysilicon layers and a dielectric layer that can be used to form linear capacitors with low voltage coefficients. The two polysilicon layers and the dielectric layer in these CMOS and BiCMOS processes may be selectively patterned in the manner discussed below (with respect to FIGS. 2A-2G, 3A-3C, 4, and 5) to fabricate high voltage transistors of the present invention. Therefore, high voltage transistors of the present invention may be fabricated without additional processing steps when using analog CMOS and BiCMOS processes that use dual polysilicon layers.